By Junjie Wu, Lian Li
This publication constitutes the refereed complaints of the eleventh Annual convention on complex machine structure, ACA 2016, held in Weihai, China, in August 2016.
The 17 revised complete papers provided have been conscientiously reviewed and chosen from 89 submissions. The papers handle matters corresponding to processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and knowledge facilities; strength and reliability; intelligence computing and cellular computing.
Read or Download Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings PDF
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Extra info for Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings
ACM (2015) 5. 5D ICs: Just a stepping stone or a long term alternative to 3d? In: Keynote Talk at 3-D Architectures for Semiconductor Integration and Packaging Conference (2011) 6. AMD: Amd radeon r9 fury x graphics card (2015). com/documents 7. : Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efﬁciency. Xilinx White paper: Vertex-7 FPGAs (2011) 8. : Noc architectures for silicon interposer systems: Why pay for more wires when you can get them (from your interposer) for free?
357–362. IEEE Press (2011) 13. : A detailed and flexible cycle-accurate network-on-chip simulator. In: 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 86–96. IEEE (2013) 14. : Throughput-effective on-chip networks for manycore accelerators. In: Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 421–432. IEEE Computer Society (2010) 15. : Analyzing CUDA workloads using a detailed GPU simulator. In: Proceedings of the International Symposium on Performance Analysis of Systems and Software, April 2009 Micro-architectural Features for Malware Detection Huicheng Peng, Jizeng Wei(B) , and Wei Guo Tianjin Advanced Network Key Lab, School of Computer Science and Technology, Tianjin University, Yaguan Road.
Qiu et al. Fig. 8. Performance comparison between baseline and 3D DRAM Cache system Power Comparison. In this section, we analysis the power consumption of the proposed design, including dynamic power and leakage power. Dynamic power results from writing and reading operations, which is determined by the total amount of the two kinds of operation. Leakage power comes from the leakage current of DRAM cells. From the results of SPEC2006, it can be seen that for last level cache, the number of writing and reading operations are not very large, thus contributing to the fact that the dynamic power consumption of our design, which is shown in Fig.